1. Field of the Invention
This invention relates to memories fabricated from charge-coupled devices, and in particular, to a serial-parallel-serial organized CCD memory utilizing interlacing and ripple clocking of the parallel shift registers to achieve a high density of bits per unit area.
2. Description of the Prior Art
Charge-coupled semiconductor devices were first invented by W. S. Boyle and G. E. Smith. (See their paper, "Charge-Coupled Semiconductor Devices," Bell Systems Tech. Journal, Vol. 49, p. 587, and U.S. Pat. No. 3,858,232.) Since that time the development of charge-coupled devices (hereinafter referred to as CCD's) has been described in numerous publications. See, e.g., the article by Gilbert F. Amelio, "Charge-Coupled Devices," Scientific American, February 1974, Volume 230, No. 2, at page 23, and C. H. Sequin and M. F. Tompsett, Charge Transfer Devices, Academic Press, Inc., 1975. An early application of CCD's to memories was disclosed in "Charge-Coupled Digital Circuit," by W. F. Kosonocky and J. E. Carnes, published in IEEE Journal of Solid-State Circuits, Vol. SC-6., p. 314, 1971.
Memory structures fabricated with CCD technology typically use one or more shift registers operating in a first-in/first-out manner where all bits are simultaneously shifted. CCD memory elements can be formed by using these shift registers directly, or in combination with other circuitry to refresh, sense, or decode. There are at least three basic arrangements of CCD memory elements: serpentine, line-addressable and serial-parallel-serial. Serial-parallel-serial (herein SPS) CCD memories have a group of parallel shift registers with an input serial shift register at one end of the group and an output serial shift register at the opposite end of the group. Data are supplied to the input serial register at a rate determined by the clock frequency of the individual elements of the register. After the register is filled a serial-to-parallel transfer operation is performed to simultaneously shift all the information out of the serial input register into the input end elements of the parallel shift registers. Clock signals applied to the parallel shift registers cause the data to transfer along the registers toward the output end of each register. When the parallel registers are filled, data are transferred into the output serial shift register at the output end of the parallel registers. Clock signals of the same frequency as those applied to the input serial register are applied to the output serial register to shift data out of the CCD memory, typically through a sense amplifier and then to other circuitry as desired.
In most CCD SPS memories there are two elements of the input shift register for each parallel shift register, where an element consists of a barrier region and a storage region. It is known in the art, e.g. Sequin, supra p. 247, that a higher packing density can be achieved by using one parallel register for each element of the input or output serial shift register. This technique is known as interlacing. Using a two-phase electrode structure for the input and output registers, the information represented by the packets of charge may be transferred into (or from) the parallel registers at the correct phase so that charges are alternately introduced into (or removed from) every other one of the parallel registers. For example, the first storage location in the even-numbered parallel registers may be loaded by data from a first transfer from the input serial register, while the first storage element of the odd-numbered parallel registers may be loaded by a second transfer from the input serial register. A corresponding procedure is followed for transfer of the data from the parallel shift registers into the output serial shift register.
The packing density of the CCD SPS may be nearly doubled again by the use of ripple clocking, also known as "electrode-per-bit operation." This technique is also known. (See Sequin, supra, p. 247-49.) In a two-phase CCD there are normally two separate potential wells per bit of storage. In conventional two-phase operation only one of each pair of wells is used to store information so that an empty well precedes and follows each well in which information is stored to provide a new empty location to which charge may be transferred. By storing information in both potential wells of each element of each shift register except for one well in a given series of wells, the packing density may be nearly doubled because data may be shifted forward by moving a blank well progressively backward along the shift register. In this manner each packet of charge is advanced one electrode as the blank well passes. The resulting motion of the charges stored in the CCD elements is slow, but in many applications the slowness is not necessarily undesirable. One such application is in serial-parallel-serial CCD memories used for storage of large quantities of information.
An SPS CCD memory utilizing both interlacing and ripple clocking of the parallel shift registers is described by S. D. Rosenbaum et al in an article entitled, "A 16,384-Bit High Density CCD Memory," published in IEEE Transactions on Electron Devices, February 1976, at page 101. A 64k-bit CCD memory with ripple clocking is described in an article entitled, "A New Multiplexed Electrode Per-Bit Structure for a 64k-Bit Charge-Coupled-Device Memory," by S. Kohyama et al, IEEE Journal of Solid-State Circuits, Vol. SC-12, No. 4, August 1977.